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[Other resource] PCI_target

Description: VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.-prepared by the PCI VHDL code, PCI2.2 compatible Xillinx Virtex II and Spantan optimized route speed, 32-bit width, the whole objective functions.
Platform: | Size: 845501 | Author: citybus | Hits:

[Other resource] pci_vhdl

Description: PCI的VHDL源码希望对大家有用！-PCI VHDL source hope useful for all!
Platform: | Size: 27890 | Author: 林建加 | Hits:

[Other resource] cpu-leon3-gr-pci-xc2v3000

Description: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的PCI位码文件及配置程序。
Platform: | Size: 417128 | Author: zhao onely | Hits:

[Other resource] pci144_vhdl

Description: PCI vhdl for Fpga designer to design PCI IP
Platform: | Size: 3617 | Author: 李晓媛 | Hits:

[VHDL-FPGA-Verilog] OpenCorespcicore

Description: PCI IP核功能实现，符合V2.2协议-realize pci function
Platform: | Size: 1203200 | Author: sophie | Hits:

[Embeded-SCM Develop] bijiaoqi

Description: pci 32位的core的实现源代码，我晕阿，实在是不好怎么说阿-pci 32-bit core of the realization of the source code, I fainted Ah, how to say it is not Arab. . . .
Platform: | Size: 30720 | Author: adfdf | Hits:

[Software Engineering] pci

Description: pci总线设计在计算机多总线结构中，PCI总线以其速度高、可靠性强、成本低及兼容性好等性能，在各种总线标准中占主导地位，而基于PCI总线标准的接口设计己成为相关项目开发中的优先选择。现阶段PCI总线设计主要采用FPGA现场可编程逻辑阵列来设计，基于FPGA不但能大大缩减电路的体积，提高电路的稳定性，而且其先进的开发工具使整个系统的设计调试周期大大缩短，基于FPGA的PCI总线设计已经成为总线设计的最主要的设计方式。 本文提出了一种基于FPGA的PCI接口的简单设计方案，简要介绍了PCI总线的特点、信号、协议与命令，分析了时序设计要点，设计了一种基于FPGA的PCI总线的方案，写出了VHDL程序并进行仿真，仿真结果证明可以成功的进行总线的读写操作。 -pci bus design
Platform: | Size: 900096 | Author: 楠楠 | Hits:

[Embeded-SCM Develop] pci.tar

Description: verilog编写的PCI总线，提供了Wishbone bus和PCI local bus之间的接口，内由两个独立的模块组成，分别完成WB BUS和PCI bus之间的传输-The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transactions originating on the PCI bus, the other one handling transactions originating on the WISHBONE bus.
Platform: | Size: 13253632 | Author: yemao | Hits:

[VHDL-FPGA-Verilog] fifo1k_32

Description: PCI 数据采集控制卡的内部 FIFO处理代码-Data Acquisition and Control Card PCI internal FIFO handling code
Platform: | Size: 2048 | Author: dalchan | Hits:

[USB develop] pci-verilog

Description: USB及PCI总线设计的一些源代码（经测试）-USB and PCI bus design some of the source code
Platform: | Size: 431104 | Author: tom | Hits:

[VHDL-FPGA-Verilog] opencore_crt

Description: 可以在Altera QuartusII下编译的Open Cores PCI桥源代码，是经过多天辛勤整理修改才完成的-Open Cores PCI bridge source code that can be compiled at Altera QuartusII. Modified under many days of hard work
Platform: | Size: 683008 | Author: Joe | Hits:

[VHDL-FPGA-Verilog] pci_32tlite_oc

Description: 嵌入式 pci总线IP core的rtl源代码，用Verilog实现-Embedded pci bus IP core of the rtl source code, Verilog realization of
Platform: | Size: 3941376 | Author: 陈达燕 | Hits:

[VHDL-FPGA-Verilog] IPcore

Description: 非常有用的IP核资源，里面包含了JTAG,MEMORY,PCI，SDRAM和USB1.1等内容，期望对大家有用-A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, and USB1.1 and other content, expectations for all of us
Platform: | Size: 903168 | Author: 李同滨 | Hits:

[Other] PCI_introduction

Description: PCI局部总线的中文介绍，非常详细，对于不想阅读英文规范的同学们很有帮助。-PCI local bus in Chinese introduction, in great detail. And it is useful to who do not want to read English.
Platform: | Size: 1134592 | Author: Sean Zhong | Hits:

[source in ebook] pci_target

Description: pci target design verilog file
Platform: | Size: 53248 | Author: peter | Hits:

[VHDL-FPGA-Verilog] pci_mini_latest.tar

Description: pci的代码，有利于关于PCI核的使用，帮助更多的人去学习-pci
Platform: | Size: 508928 | Author: yly | Hits:

[VHDL-FPGA-Verilog] pci_steuerung_target

Description: vhdl code for card pci to fpga
Platform: | Size: 7168 | Author: sina | Hits:

[VHDL-FPGA-Verilog] pci_steuerung_master

Description: vhdl code for card pci to fpga
Platform: | Size: 4096 | Author: sina | Hits:

[VHDL-FPGA-Verilog] fpga_A

Description: vhdl code for card pci to fpga
Platform: | Size: 3072 | Author: sina | Hits:

[VHDL-FPGA-Verilog] RED--PCI-5.0

Description: 使用PCI9054作为接口芯片，通过FPGA实现PCI9054，SDRAM和AD之间的连接，本程序是以此为目的编写的.-PCI9054 interface chip used as a through FPGA implementation PCI9054, SDRAM, and the connection between AD, the program is prepared for this purpose.
Platform: | Size: 3389440 | Author: 黄宸懿 | Hits:
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